1. Field of the Invention
The present invention pertains to buses for synchronous dynamic random access memory (“SDRAM”) and, more particularly, to a double data rate (“DDR”) SDRAM bus design that is scalable with frequency.
2. Description of the Related Art
One continually evolving computing system characteristic is “speed.” In a vernacular sense, “speed” is simply a measure of a computing system's power, or ability to handle large amounts of data or execute sophisticated applications. In a more technical sense, speed is measured by the number of operations performed or instructions executed per second. Either way, faster speeds are typically considered more desirable because they imply increased performance in a computing system.
A computing system's speed is a function of many aspects of its design. The general public tends to focus on processor clock speed because of its significance in the performance of personal computers. Furthermore, processor clock speeds continually reach previously unattainable speeds on a regular basis, thereby fueling the public's interest. However, processor clock speed is but one factor in the speed of the computing system as a whole. Another important factor is the speed of the memory subsystem used by the processor. If the processor races far beyond the speeds attainable by the memory subsystem, the processor's excess speed results only in unrealized potential as opposed to actual performance.
Computer engineers and architects consequently devote as much effort to improving the performance of memory subsystems as they do processors. Memory subsystems frequently employ “memory modules” that typically includes multiple memory devices mounted to one or more printed circuit boards and configured into a single portion of the memory subsystem. Some memory modules are “dual in-line” memory modules (“DIMMs”) and some are “single in-line” memory modules (“SIMMs”). The principal difference between DIMMs and SIMMs is that processors and controllers access SIMMs over a bus that is 32 bits wide, but access DIMMs over a bus that is 64 bits wide.
One memory technology common today is called Synchronous Dynamic Random Access Memory (“SDRAM”). SDRAM actually synchronizes its operation with the processor using the signals on the processor's bus. SDRAM implementations are generally capable of running at 133 MHz, which is relatively fast compared to other commonly used memory technologies. SDRAM has several features that improve performance relative to other dynamic random access memory (“DRAM”) technologies. For instance, the memory devices are arranged in “banks” that alternate during an access so that some functions can be performed in parallel rather than in serial. SDRAM is also capable of “bursting” data, which permits greater data output rates.
Under pressure from the constant demand to improve performance, designers have developed an SDRAM known as double data rate synchronous dynamic random access memory (“DDR SDRAM”). DDR SDRAM is structured and functions similarly to regular SDRAM, but doubles the bandwidth of the memory by transferring data twice per cycle—on both the rising and falling edges of the clock signal. In conventional SDRAM, only one or the other of the falling and rising edges can trigger a data transfer, but, in DDR SDRAM, both are used. Thus, DDR SDRAM can essentially transfer twice as much data in a given period of time as can conventional SDRAM.
Even such an improvement as DDR SDRAM can have only limited impact on overall performance of a computing system, however. For instance, no matter how fast the processor(s) and memory subsystem are, the system as a whole can be no faster than the bus, or connection, between them. With SDRAM and DDR SDRAM, one performance limitation is the physical length of the bus, and especially the traces of the bus, between the processor(s) and the devices of the memory modules. Each unit length of the bus creates a “propagation delay.” Longer buses have greater the propagation delays that slow their performance. High speed buses consequently need to be short. As the pressure for faster operation grows, the length of these buses decreases.
One of the many problems associated with this phenomenon is it hampers the applicability of the SDRAM technology. Because the buses must be short, SDRAM is relatively difficult to use in memory intensive computing systems, e.g., servers. Such systems employ large memory subsystems with many memory modules, which requires long buses that induce large propagation delays. To counteract this problem, computer architectures employ repeaters, and or buffer chips. These solutions raise additional complications, however, such as increased complexity and higher cost. In other words, the SDRAM technology is not very scalable to large memory subsystems because of the physical limitations of the traces and the bus.